The present invention relates to a programmable digital clock signal frequency divider module and a modular digital clock signal frequency divider circuit for dividing a system clock signal, and, more specifically, to a programmable digital clock signal frequency divider module suitable for use in a prescaler architecture and modular digital clock signal frequency divider circuits that have a prescaler architecture.
Many digital electronic circuits require one or more digital clock signals in order to function. There are numerous types of digital clock signals such as short constant frequency pulsed signals, irregular frequency pulsed signals, clock signals with uneven duty cycles and clock signals with a 50% duty cycle. For high speed circuits, such as dual data rate circuits, it is highly desirable to use digital clock signals with a 50% duty cycle. One option for creating different clock signals is by using a modular programmable digital clock signal frequency divider circuit having series connected modules (cells). The modular programmable digital clock signal frequency divider circuit has a prescaler architecture that can be programmed to convert an input digital clock signal into one of many lower frequency output digital clock signals. The prescaler architecture that does not have long delay loops as feedback is essentially only present within a module or between adjacent modules. However, such divider circuits may not be able to provide a 50% duty cycle for every one of the lower frequency output digital clock signals.